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rev. pre 17 dec 02 preliminary technical data preliminary technical data information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7450a/AD7440 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 differential input, 1msps, 12- & 10-bit adcs in 8-lead sot-23 features fast throughput rate: 1msps specified for v dd of 3 v and 5 v low power at max throughput rate: 3.75 mw typ at 1msps with 3 v supplies 9 mw typ at 1msps with 5 v supplies fully differential analog input wide input bandwidth: 70db sinad at 200khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface - spi tm /qspi tm / microwire tm / dsp compatible power-down mode: 1a max 8 lead sot-23 and msop packages applications transducer interface battery powered systems data acquisition systems portable instrumentation motor control communications general description the ad7450a/AD7440 are respectively 12- and 10-bit, high speed, low power, successive-approximation (sar) analog-to-digital converters that feature a fully differential analog input. these parts operate from a single 3 v or 5 v power supply and feature throughput rates up to 1msps. the parts contains a low-noise, wide bandwidth, differen- tial track and hold amplifier (t/h) which can handle input frequencies in excess of 1mhz with the -3db point being 20mhz typically. the reference voltage is applied externally to the v ref pin and can be varied from 100 mv to 3.5 v depending on the power supply and what suits the application. the value of the reference voltage determines the common mode voltage range of the part. with this truly differential input structure and variable reference input, the user can select a variety of input ranges and bias points. the conversion process and data acquisition are controlled using cs and the serial clock allowing the device to inter- face with microprocessors or dsps. the input signals are sampled on the falling edge of cs and the conversion is also initiated at this point. functional block diagram the sar architecture of these parts ensures that there are no pipeline delays. the ad7450a and the AD7440 use advanced design tech- niques to achieve very low power dissipation at high throughput rates. product highlights 1.operation with either 3 v or 5 v power supplies. 2.high throughput with low power consumption. with a 3v supply, the ad7450a/AD7440 offer 3.75mw typ power consumption for 1msps throughput. 3.fully differential analog input. 4.flexible power/serial clock speed management. the conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. these parts also feature a shutdown mode to maximize power efficiency at lower throughput rates. 5.variable voltage reference input. 6.no pipeline delay. 7.accurate control of the sampling instant via a cs input and once off conversion control. 8. enob > 8 bits typically with 100mv reference. microwire is a trademark of national semiconductor corporation. spi and qspi are trademarks of motorola, inc. 12-bit successive approximation adc control logic ad7450a/ AD7440 v in+ v in- v ref gnd sclk s data v dd t/h
rev. pre preliminary technical data ?2? parameter test conditions/comments a version b version 1 unit dynamic performance f in = 200khz signal to (noise + distortion) (sinad) 2 v dd = 4.75v to 5.25v 70 70 db min v dd = 2.7 v to 3.6v 68 68 db min total harmonic distortion (thd) 2 v dd = 4.75v to 5.25v, -80db typ -75 -75 db max v dd = 2.7v to 3.6v, -78db typ -73 -73 db max peak harmonic or spurious noise 2 v dd = 4.75v to5.25v, -82db typ -75 -75 db max v dd = 2.7v to 3.6v, -80db typ -73 -73 db max intermodulation distortion (imd) 2 second order terms -85 -85 db typ third order terms -85 -85 db typ aperture delay 2 10 10 ns typ aperture jitter 2 50 50 ps typ full power bandwidth 2 @ -3 db 20 20 mhz typ @ -0.1 db 2.5 2.5 mhz typ dc accuracy resolution 12 12 bits integral nonlinearity (inl) 2 2 2 lsb max differential nonlinearity (dnl) 2 guaranteed no missed codes to 12 bits. -1/+2 1 lsb max zero code error 2 v dd = 4.75v to 5.25v 3 3 lsb max v dd = 2.7v to 3.6v 6 6 lsb max positive gain error 2 v dd = 4.75v to 5.25v 3 3 lsb max v dd = 2.7v to 3.6v 6 6 lsb max negative gain error 2 v dd = 4.75v to 5.25v 3 3 lsb max v dd = 2.7v to 3.6v 6 6 lsb max analog input full scale input span 2 x v ref 4 v in+ - v in - v in+ - v in - v absolute input voltage v in+ v cm = v ref v cm 3 v ref /2 v cm 3 v ref /2 v v in- v cm = v ref v cm 3 v ref /2 v cm 3 v ref /2 v dc leakage current 1 1 a max input capacitance when in track 20 20 pf typ when in hold 6 6 pf typ reference input v ref input voltage v dd = 4.75v to 5.25v (1% tolerance for specified performance) 2.5 5 2.5 5 v v dd = 2.7v to 3.6v (1% tolerance for specified performance) 2.0 6 2.0 6 v dc leakage current 1 1 a max v ref input capacitance 15 15 pf typ logic inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current, i in typically 10na, v in = 0vorv dd 1 1 a max input capacitance, c in 7 10 10 pf max logic outputs output high voltage, v oh v dd = 4.75v to 5.25v i source = 200a 2.8 2.8 v min v dd = 2.7v to 3.6v i source = 200a 2.4 2.4 v min output low voltage, v ol i sink =200a 0.4 0.4 v max floating-state leakage current 1 1 a max floating-state output capacitance 7 10 10 pf max output coding two?s two?s complement comlement ad7450a - specifications 1 ( v dd = 2.7v to 3.6v, f sclk = 18mhz, f s = 1msps, v ref = 2.0 v; v dd = 4.75v to 5.25v, f sclk = 18mhz, f s = 1msps, v ref = 2.5 v; v cm 3 = v ref ; t a = t min to t max , unless otherwise noted.)
rev. pre preliminary technical data ?3? ad7450a/AD7440 parameter test conditions/comments a version b version 1 units conversion rate conversion time 888ns with an 18mhz sclk 16 16 sclk cycles track/hold acquisition time 2, 7 sine wave input 200 200 ns max step input t b d t b d ns max throughput rate 9 1 1 msps max power requirements v dd range: 3 v+20%/-10%; 5 v 5% 2.7v/5.25v 2.7v/5.25v vm in/max i dd 8,10 normal mode(static) sclk on or off 0.5 0.5 ma typ normal mode (operational) v dd = 4.75v to 5.25v 1.38mw typ for 100ksps 8 1.8 1.8 ma max v dd = 2.7v to 3.6v 0.53mw typ for 100ksps 8 1.25 1.25 ma max full power-down mode sclk on or off 1 1 a max power dissipation normal mode (operational) v dd =5 v. 9 9 mw max v dd =3 v. 3.75 3.75 mw max full power-down v dd =5 v. sclk on or off 5 5 w max v dd =3 v. sclk on or off 3 3 w max notes 1 temperature ranges as follows: a and b versions: ?40c to +85c. 2 see ?terminology? section. 3 common mode voltage. the input signal can be centered on any choice of dc common mode voltage as long as this value is in the range specified in figures tbd and tbd. 4 because the input spans of v in+ and v in- are both v ref , and they are 180 out of phase, the differential voltage is 2 x v ref . 5 the ad7450a is functional with a reference input from100mv and for v dd = 5v, the reference can range up to 3.5v. 6 the ad7450a is functional with a reference input from100mv and for v dd = 3v, the reference range up to 2.2v. 7 sample tested @ +25c to ensure compliance. 8 see power versus throughput rate section. 9 see ?serial interface section?. 10 measured with a midscale dc input. specifications subject to change without notice. ad7450a - specifications 1
rev. pre preliminary technical data ?4? parameter test conditions/comments b version 1 unit dynamic performance f in = 200khz signal to (noise + distortion) (sinad) 2 v dd = 4.75v to 5.25v 61 db min v dd = 2.7v to 3.6v 61 db min total harmonic distortion (thd) 2 v dd = 4.75v to 5.25v, -80db typ -73 db max v dd = 2.7v to 3.6v, -78db typ -73 db max peak harmonic or spurious noise 2 v dd = 4.75v to 5.25v, -82db typ -73 db max v dd = 2.7v to 3.6v, -80db typ -73 db max intermodulation distortion (imd) 2 second order terms -78 db typ third order terms -78 db typ aperture delay 2 10 ns typ aperture jitter 2 50 ps typ full power bandwidth 2 @ -3 db 20 mhz typ @ -0.1 db 2.5 mhz typ dc accuracy resolution 10 bits integral nonlinearity (inl) 2 0.5 lsb max differential nonlinearity (dnl) 2 guaranteed no missed codes to 10 bits. 0.5 lsb max zero code error 2 v dd = 4.75v to 5.25v 1.5 lsb max v dd = 2.7v to 3.6v 3 lsb max positive gain error 2 v dd = 4.75v to 5.25v 1.5 lsb max v dd = 2.7v to 3.6v 3 lsb max negative gain error 2 v dd = 4.75v to 5.25v 1.5 lsb max v dd = 2.7v to 3.6v 3 lsb max analog input full scale input span 2 x v ref 4 v in+ - v in - v absolute input voltage v in+ v cm = v ref v cm 3 v ref /2 v v in- v cm = v ref v cm 3 v ref /2 v dc leakage current 1 a max input capacitance when in track 20 pf typ when in hold 6 pf typ reference input v ref input voltage v dd = 4.75v to 5.25v (1% tolerance for specified performance) 2.5 5 v v dd = 2.7v to 3.6v (1% tolerance for specified performance) 2.0 6 v dc leakage current 1 a max v ref input capacitance 15 pf typ logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i in typically 10na, v in = 0vorv dd 1 a max input capacitance, c in 7 10 pf max logic outputs output high voltage, v oh v dd = 4.75v to 5.25v i source = 200a 2.8 v min v dd = 2.7v to 3.6v i source = 200a 2.4 v min output low voltage, v ol i sink =200a 0.4 v max floating-state leakage current 1 a max floating-state output capacitance 7 10 pf max output coding two?s complement AD7440 - specifications 1 ( v dd = 2.7v to 3.6v, f sclk = 18mhz, f s = 1msps, v ref = 2.0 v; v dd = 4.75v to 5.25v, f sclk = 18mhz, f s = 1msps, v ref = 2.5 v; v cm 3 = v ref ; t a = t min to t max , unless otherwise noted.)
rev. pre preliminary technical data ?5? ad7450a/AD7440 parameter test conditions/comments b version 1 units conversion rate conversion time 888ns with an 18mhz sclk 16 sclk cycles track/hold acquisition time 2 sine wave input 200 ns max step input t b d ns max throughput rate 9 1 msps max power requirements v dd range: 3 v+20%/-10%; 5 v 5% 2.7v/5.25v vm in/max i dd 8,10 normal mode(static) sclk on or off 0.5 ma typ normal mode (operational) v dd = 4.75v to 5.25v 1.38mw typ for 100ksps 8 1.8 ma max v dd = 2.7 v to 3.6v 0.53mw typ for 100ksps 8 1.25 ma max full power-down mode sclk on or off 1 a max power dissipation normal mode (operational) v dd =5 v. 9 mw max v dd =3 v. 3.75 mw max full power-down v dd =5 v. sclk on or off 5 w max v dd =3 v. sclk on or off 3 w max notes 1 temperature ranges as follows: b versions: ?40c to +85c. 2 see ?terminology? section. 3 common mode voltage. the input signal can be centered on any choice of dc common mode voltage as long as this value is in the range specified in figures tbd and tbd. 4 because the input spans of v in+ and v in- are both v ref , and they are 180 out of phase, the differential voltage is 2 x v ref . 5 the AD7440 is functional with a reference input from100mv and for v dd = 5v, the reference can range up to 3.5v. 6 the AD7440 is functional with a reference input from100mv and for v dd = 3v, the reference range up to 2.2v. 7 sample tested @ +25c to ensure compliance. 8 see power versus throughput rate section. 9 see ?serial interface section?. 10 measured with a midscale dc input. specifications subject to change without notice. AD7440 - specifications 1
rev. pre preliminary technical data ?6? limit at t min , t max parameter 2.7v-3.6v 4.75v-5.25v units description f sclk 4 10 10 khz min 18 18 mhz max t convert 16 x t sclk 16 x t sclk t sclk = 1/f sclk 888 888 ns max t quiet 25 25 ns min minimum quiet time between the end of a serial read and the next falling edge of cs t 1 10 10 ns min minimum cs pulsewidth t 2 10 10 ns min cs falling edge to sclk falling edge setup time t 3 5 20 20 ns max delay from cs falling edge until sdata 3-state disabled t 4 5 40 40 ns max data access time after sclk falling edge t 5 0.4 t sclk 0.4 t sclk ns min sclk high pulse width t 6 0.4 t sclk 0.4 t sclk ns min sclk low pulse width t 7 10 10 ns min sclk edge to data valid hold time t 8 6 10 10 ns min sclk falling edge to sdata 3-state enabled 35 35 ns max sclk falling edge to sdata 3-state enabled t power-up 7 1 1 s max power-up time from full power-down notes 1 sample tested at +25c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 volts. 2 see figure 1, figure 2 and the ?serial interface? section. 3 common mode voltage. 4 mark/space ratio for the sclk input is 40/60 to 60/40. 5 measured with the load circuit of figure 3 and defined as the time required for the output to cross 0.8 v or 2.4 v with v dd = 5 v and time for an output to cross 0.4 v or 2.0 v for v dd = 3 v. 6 t 8 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 2. the meas ured num- ber is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 8 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7 see ?power-up time? section. specifications subject to change without notice. timing specifications 1,2 ( v dd = 2.7v to 3.6v, f sclk = 18mhz, f s = 1msps, v ref = 2.0 v; v dd = 4.75v to 5.25v, f sclk = 18mhz, f s = 1msps, v ref = 2.5 v; v cm 3 = v ref ; t a = t min to t max , unless otherwise noted.) figure 1. ad7450a serial interface timing diagram figure 2. AD7440 serial interface timing diagram ad7450a/AD7440 1 2345 13 16 15 14 t 3 00 0 0 db11 db10 db2 db1 db0 t 2 4 leading zero?s 3 - s t ate t 4 t 6 t 5 t 7 t 8 t quiet convert t sclk sdata t 1 1 2345 13 16 15 14 t 3 00 0 0 db9 db8 db0 0 0 t 2 4 leading zero?s 3-state t 4 t 6 t 5 t 7 t 8 t quiet convert t b sclk sdata t 1 2 trailing zeros
rev. pre preliminary technical data ?7? ad7450a/AD7440 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7450a/AD7440 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 (t a = +25c unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . -0.3 v to +7 v v in+ to gnd . . . . . . . . . . . . . . . . . ?0.3 v to v dd + 0.3 v v in- to gnd . . . . . . . . . . . . . . . ?0.3 v to v dd + 0.3 v digital input voltage to gnd . . . . . . . . -0.3 v to +7 v digital output voltage to gnd . -0.3 v to v dd + 0.3 v v ref to gnd . . . . . . . . . . . . . . . . . -0.3 v to v dd +0.3 v input current to any pin except supplies 2 . . . . 10ma operating temperature range commercial (b version) . . . . . . . . . . . -40 o c to +85 o c storage temperature range . . . . . . . . . -65 o c to +150 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . +150 o c ja thermal impedance . . . . . . . . . . 205.9c/w (msop) 211.5c/w (sot-23) jc thermal impedance . . . . . . . . . 43.74c/w (msop) 91.99c/w (sot-23) lead temperature, soldering vapor phase (60 secs) . . . . . . . . . . . . . . . . . . . +215 o c infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . +220 o c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.5kv notes 1 stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch up. linearity package model range error (lsb) 1 option 4 branding information ad7450abrt -40c to +85c 1 lsb rt-8 csb ad7450aart -40c to +85c 2 lsb rt-8 csa ad7450abrm -40c to +85c 1 lsb rm-8 csb ad7450aarm -40c to +85c 2 lsb rm-8 csa AD7440brt -40c to +85c 0.5 lsb rt-8 ctb AD7440brm -40c to +85c 0.5 lsb rm-8 ctb tbd evaluation board eval-control brd2 3 controller board ordering guide notes 1 linearity error here refers to integral non-linearity error. 2 this can be used as a stand-alone evaluation board or in conjunction with the evaluation board controller for evaluation/demons tration purposes. 3 evaluation board controller. this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. to order a complete evaluation kit, you will need to order the adc evaluation b oard i.e. tbd, the eval-control brd2 and a 12v ac transformer. see the tbd technote for more information. 4 rt = sot-23; rm = msop figure 3. load circuit for digital output timing specifications

rev. pre preliminary technical data ?8? ad7450a/AD7440 pin configuration 8-lead msop pin function description pin mnemonic function v ref reference input for the ad7450a/AD7440. an external reference must be applied to this input. for a 5 v power supply, the reference is 2.5 v (1%) and for a 3 v power supply, the reference is 2v (1%) for specified performance. this pin should be decoupled to gnd with a capacitor of at least 0.1f. see the ?reference section? for more details. v in+ positive terminal for differential analog input. v in- negative terminal for differential analog input. g n d analog ground. ground reference point for all circuitry on the ad7450a/AD7440. all analog input signals and any external reference signal should be referred to this gnd voltage. cs chip select. active low logic input. this input provides the dual function of initiating a conversion on the ad7450a/AD7440 and framing the serial data transfer. sdata serial data. logic output. the conversion result from the ad7450a/AD7440 is provided on this out- put as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream of the ad7450a consists of four leading zeros followed by the 12 bits of conversion data which are provided msb first; the data stream of the AD7440 consists of four leading zeros, followed by the 10-bits of conversion data, followed by two trailing zeros. in both cases, the output coding is two?s complement. sclk serial clock. logic input. sclk provides the serial clock for accessing data from the part. this clock input is also used as the clock source for the conversion process. v dd power supply input. v dd is 3 v (+20%/-10%) or 5 v (5%). this supply should be decoupled to gnd with a 0.1f capacitor and a 10f tantalum capacitor. pin configuration 8-lead sot-23 ad7450a/AD7440 sot-23 (not to scale) top view 1 2 3 4 5 6 7 8 v ref v in + v in - gnd sdata sclk v dd ad7450a/AD7440 msop (not to scale) top view 1 2 3 4 5 6 7 8 v ref v in + v in - gnd sdata sclk v dd
rev. pre preliminary technical data ?9? ad7450a/AD7440 terminology signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit con- verter with a sine wave input is given by: signal to ( noise + distortion ) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db and for a 10-bit converter, this is 62db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7450, it is defined as: thd (db ) = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second to the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms in- clude (fa + fb) and (fa ? fb), while the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb) and (fa ? 2fb). the ad7450a/AD7440 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a fre- quency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. aperture delay this is the amount of time from the leading edge of the sampling clock until the adc actually takes the sample. aperture jitter this is the sample to sample variation in the effective point in time at which the actual sample is taken. full power bandwidth the full power bandwidth of an adc is that input fre- quency at which the amplitude of the reconstructed fundamental is reduced by 0.1db or 3db for a full scale input. common mode rejection ratio (cmrr) the common mode rejection ratio is defined as the ratio of the power in the adc output at full-scale fre- quency, f, to the power of a 200mv p-p sine wave applied to the common mode voltage of v in+ and v in- of fre- quency fs: cmrr (db) = 10log(pf/pfs) pf is the power at the frequncy f in the adc output; pfs is the power at frequency fs in the adc output. integral nonlinearity (inl) this is the maximum deviation from a straight line pass- ing through the endpoints of the adc transfer function. differential nonlinearity (dnl) this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. zero code error this is the deviation of the midscale code transition (111...111 to 000...000) from the ideal v in+ -v in - (i.e., 0lsb). positive gain error this is the deviation of the last code transition (011...110 to 011...111) from the ideal v in+ -v in- (i.e., +v ref - 1lsb), after the zero code error has been adjusted out. negative gain error this is the deviation of the first code transition (100...000 to 100...001) from the ideal v in+ -v in - (i.e., -v ref + 1lsb), after the zero code error has been adjusted out. track/hold acquisition time the track/hold acquisition time is the minimum time required for the track and hold amplifier to remain in track mode for its output to reach and settle to within 0.5 lsb of the applied input signal. power supply rejection ratio (psrr) the power supply rejection ratio is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 200mv p-p sine wave applied to the adc v dd supply of frequency fs. the frequency of this input varies from 1khz to 1mhz. psrr (db) = 10 log (pf/pfs) pf is the power at frequency f in the adc output; pfs is the power at frequency fs in the adc output.
rev. pre preliminary technical data ?10? ad7450a/AD7440 performance curves (default conditions: ta = 25c, fs = 1msps, fsclk = 18mhz) tpc 1. ad7450a sinad vs analog input frequency for various supply voltages tpc 2 shows the common mode rejection ratio versus v dd supply ripple frequency for both v dd = 5v and 3 v. here a 200mv p-p sine wave is coupled onto the common mode voltage of v in+ and v in- . tpc 2. ad7450a cmrr versus frequency for v dd = 5v and 3 v tpc 3 and tpc 4 shows the power supply rejection ratio (see terminology) versus v dd supply ripple fre- quency for the ad7450a/AD7440 with and without power supply decoupling respectively. tpc 3. ad7450a psrr vs. supply ripple frequency without supply decoupling tpc 4. ad7450a psrr vs. supply ripple frequency with supply decoupling of tbd ad7450a performance curves (default conditions: ta = 25c, fs = 1msps, fsclk = 18mhz) tpc 5. ad7450a dynamic performance with v dd =5v
rev. pre preliminary technical data ?11? ad7450a/AD7440 tpc 6. typical dnl for the ad7450a for v dd = 5v tpc 7. typical inl for the ad7450a for v dd = 5v

tpc 8. change in dnl vs. v ref for the ad7450a for v dd = 5v

tpc 9. change in dnl vs. v ref for the ad7450a for v dd = 3 v

tpc 10. change in inl vs. v ref for the ad7450a for v dd = 5v

tpc 11. change in inl vs. v ref for the ad7450a for v dd = 3 v
rev. pre preliminary technical data ?12? ad7450a/AD7440 tpc 12. change in zero code error vs reference voltage v dd = 5v and 3 v for the ad7450a

tpc 13 change in enob vs reference voltage v dd = 5v and 3 v for the ad7450a tpc 14. histogram of 10000 conversions of a dc input for the ad7450a with v dd = 5v AD7440 performance curves (default conditions: ta = 25c, fs = 1msps, fsclk = 18mhz) tpc 15. AD7440 dynamic performance with v dd =5v tpc 15. typical dnl for the AD7440 for v dd = 5v tpc 16. typical inl for the AD7440 for v dd = 5v
rev. pre preliminary technical data ?13? ad7450a/AD7440 circuit information the ad7450a/AD7440 are 12- and 10- bit, fast, low power, single supply, successive approximation analog-to- digital converters (adc). they can operate with a 5 v and 3 v power supply and are capable of throughput rates up to 1msps when supplied with an 18mhz sclk. they require an external reference to be applied to the v ref pin, with the value of the reference chosen depending on the power supply and what suits the application. the ad7450a/AD7440 requires an external reference. when operated with a 5 v supply, the maximum reference that can be applied is 3.5 v and when operated with a 3 v supply, the maximum reference that can be applied is 2.2 v. (see ?reference section?). the ad7450a/AD7440 has an on-chip differential track and hold amplifier, a successive approximation (sar) adc and a serial interface, housed in either an 8-lead sot-23 or msop package. the serial clock input ac- cesses data from the part and also provides the clock source for the successive-approximation adc. the ad7450a/ AD7440 feature a power-down option for reduced power consumption between conversions. the power-down fea- ture is implemented across the standard serial interface as described in the ?modes of operation? section. converter operation the ad7450a/AD7440 is a successive approximation adc based around two capacitive dacs. figures 4 and 5 show simplified schematics of the adc in acquisition and conversion phase respectively. the adc comprises of control logic, a sar and two capacitive dacs. in fig- ure 4 (acquisition phase), sw3 is closed and sw1 and sw2 are in position a, the comparator is held in a bal- anced condition and the sampling capacitor arrays acquire the differential signal on the input sw3 v in+ v in- sw1 c s c s a a b v ref sw2 control logic capacitive dac capacitive dac comparator b figure 4. adc acquisition phase when the adc starts a conversion (figure 5), sw3 will open and sw1 and sw2 will move to position b, causing the comparator to become unbalanced. both inputs are disconnected once the conversion begins. the control logic and the charge redistribution dacs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a bal- anced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc?s output code. the output impedances of the sources driving the v in+ and the v in- pins must be matched otherwise the two inputs will have different set- tling times, resulting in errors. sw3 v in+ v in- sw1 c s c s a b a b v ref sw2 control logic capacitive dac capacitive dac comparator figure 5. adc conversion phase adc transfer function the output coding for the ad7450a/AD7440 is two?s complement. the designed code transitions occur at suc- cessive lsb values (i.e. 1lsb, 2lsbs, etc.). the lsb size of the ad7450a is 2xv ref /4096 and the lsb size of the AD7440 is 2xv ref /1024. the ideal transfer character- istic of the ad7450a/AD7440 is shown in figure 6. 100...000 +v ref - 1lsb 100...001 100...010 111...111 000...000 000...001 011...110 011...111 -v ref + 1lsb 0lsb adc code 1lsb = 2xv ref /4096 (ad7450a) ilsb = 2xv ref /1024 (AD7440) analog input (v in+ - v in- ) figure 6. ad7450a/AD7440 ideal transfer characteristic typical connection diagram figure 7 shows a typical connection diagram for the ad7450a/AD7440 for both 5 v and 3 v supplies. in this
rev. pre preliminary technical data ?14? ad7450a/AD7440 setup the gnd pin is connected to the analog ground plane of the system. the v ref pin is connected to either a 2.5 v or a 2 v decoupled reference source depending on the power supply, to set up the analog input range. the common mode voltage has to be set up externally and is the value that the two inputs are centered on. the conver- sion result is output in a 16-bit word with four leading zeros followed by the msb of the 12-bit or 10-bit result. the 10-bit result of the AD7440 is followed by two trail- ing zeros. for more details on driving the differential inputs and setting up the common mode, see the ?driving differential inputs? section. cm* cm* * cm - common mode voltage v in+ v in- v dd sclk sdata gnd v ref c/p serial interface +3v/+5v supply 2v/2.5v vref 0.1f 0.1f 10f ad7450a/AD7440 v ref p-to-p v ref p-to-p figure 7. typical connection diagram the analog input the analog input of the ad7450a/AD7440 is fully differ- ential. differential signals have a number of benefits over single ended signals including noise immunity based on the device?s common mode rejection, improvements in distortion performance, doubling of the device?s available dynamic range and flexibility in input ranges and bias points. figure 8 defines the fully differential analog input of the ad7450a/AD7440. v in+ ad7450a/ AD7440 v in- v ref p-to-p v ref p-to-p common mode voltage figure 8. differential input definition the amplitude of the differential signal is the difference between the signals applied to the v in+ and v in- pins (i.e. v in+ - v in- ). v in+ and v in- are simultaneously driven by two signals each of amplitude v ref that are 180 out of phase. the amplitude of the differential signal is therefore -v ref to +v ref peak-to-peak (i.e. 2 x v ref ). this is re- gardless of the common mode (cm). the common mode is the average of the two signals, i.e. (v in+ + v in- )/2 and is therefore the voltage that the two inputs are centered on. this results in the span of each input being cm v ref /2. this voltage has to be set up externally and its range var- ies with v ref . as the value of v ref increases, the common mode range decreases. when driving the inputs with an amplfier, the actual common mode range will be determined by the amplifier?s output voltage swing. figures 9 and 10 show how the common mode range typi- cally varies with v ref for both a 5 v and a 3 v power supply. the common mode must be in this range to guar- antee the functionality of the ad7450a/AD7440. for ease of use, the common mode can be set up to be equal to v ref , resulting in the differential signal being v ref centered on v ref . when a conversion takes place, the common mode is rejected resulting in a virtually noise free signal of amplitude -v ref to +v ref corresponding to the digital codes of 0 to 4095 in the case of the ad7450a and 0 to 1024 in the case of the AD7440.

figure 9. input common mode range versus v ref (v dd = 5v and v ref (max) = 3.5v)
rev. pre preliminary technical data ?15? ad7450a/AD7440

figure 10. input common mode range versus v ref (v dd = 3v and v ref (max) = 2v) figure 11 shows examples of the inputs to v in+ and v in- for different values of v ref for v dd = 5 v. it also gives the maximum and minimum common mode voltages for each reference value according to figure 9. reference = 1.25 v (v ref max/2) 1.25 v peak to peak common mode (cm) cm min = 0.625 v cm max = 4.42 v reference = 2.5 v (v ref max) 2.5 v peak to peak common mode (cm) cm min = 1.25 v cm max = 3.75 v v in- v in+ v in+ v in- figure 11. examples of the analog inputs to v in+ and v in- for different values of v ref for v dd = 5 v. analog input structure figure 12 shows the equivalent circuit of the analog input structure of the ad7450a/AD7440. the four diodes provide esd protection for the analog inputs. care must be taken to ensure that the analog input signals never ex- ceed the supply rails by more than 300mv. this will cause these diodes to become forward biased and start conducting into the substrate. these diodes can conduct up to 10ma without causing irreversible damage to the part. the capacitors c1, in figure 12 are typically 4pf and can primarily be attributed to pin capacitance. the resistors are lumped components made up of the on-resis- tance of the switches. the value of these resistors is typically about 100 . the capacitors, c2, are the adc?s sampling capacitors and have a capacitance of 16pf typi- cally. for ac applications, removing high frequency components from the analog input signal is recommended by the use of an rc low-pass filter on the relevant analog input pins. in applications where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances will significantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of the opamp will be a function of the particu- lar application. v dd c1 d d v in+ r1 c2 v in- r1 c2 v dd d d c1 figure 12. equivalent analog input circuit. conversion phase - switches open track phase - switches closed when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance will depend on the amount of total harmonic distortion (thd) that can be tolerated. the thd will increase as the source impedance increases and performance will degrade. figure 13 shows a graph of the thd versus analog input signal frequency for dif- ferent source impedances for both v dd = 5 v and 3 v. figure 13.thd vs analog input frequency for various source impedances for v dd = 5v and 3 v
rev. pre preliminary technical data ?16? ad7450a/AD7440 figure 14 shows a graph of thd versus analog input frequency for v dd of 5 v 5% and 3 v +20/-10%, while sampling at 1msps with a sclk of 18 mhz. in this case the source impedance is 10 . figure 14.thd vs analog input frequency for 3v and 5v supply voltages driving differential inputs differential operation requires that v in+ and v in- be si- multaneously driven with two equal signals that are 180 o out of phase. the common mode must be set up exter- nally and has a range which is determined by v ref , the power supply and the particular amplifier used to drive the analog inputs (see figures 9 and 10). differential modes of operation with either an ac or dc input, provide the best thd performance over a wide frequency range. since not all applications have a signal preconditioned for differ- ential operation, there is often a need to perform single ended to differential conversion. differential amplifier an ideal method of applying differential drive to the ad7450a/ AD7440 is to use a differential amplifier such as the ad8138. this part can be used as a single ended to differential amplifier or as a differential to differential amplifier. in both cases the analog input needs to be bipolar. it also provides common mode level shifting and buffering of the bipolar input signal. figure 15 shows how the ad8138 can be used as a single ended to differential amplifier. the positive and negative outputs of the ad8138 are connected to the respec- tive inputs on the adc via a pair of series resistors to minimize the effects of switched capacitance on the front end of the adcs. the rc low pass filter on each analog input is recommended in ac applications to remove high frequency components of the analog input. the architecture of the ad8138 results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components. if the analog input source being used has zero impedance then all four resistors (rg1, rg2, rf1, rf2) should be the same. if the source has a 50 impedance and a 50 termination for example, the value of rg2 should be increased by 25 to balance this parallel impedance on the input and thus ensure that both the positive and negative analog inputs have the same gain (see figure 15). the outputs of the amplifier are perfectly matched, balanced differential outputs of identical amplitude and are exactly 180 o out of phase. the ad8138 is specified with 3 v, 5 v and 5 v power supplies but the best results are obtained when it is supplied by 5 v. a lower cost device that could also be used in this configuration with slight differences in characteristics to the ad8138 but with similar performance and operation is the ad8132. 2.5v 3.75v 1.25v rs* rs* rf2 2.5v 3.75v 1.25v external v ref (2.5v) v ref v in+ ad7450a/ AD7440 v in- ad8138 c* c* *mount as close to the ad7450a/AD7440 as possible and ensure high precision rs and cs are used rs - 50r; c - 1nf; rg1=rf1=rf2= 499r; rg2 = 523r rf1 rg1 v ocm 51r rg2 gnd +2.5v -2.5v figure 15. using the ad8138 as a single ended to differential amplifier opamp pair an opamp pair can be used to directly couple a differential signal to the ad7450a/AD7440. the circuit configura- tions shown in figures 16(a) and 16(b) show how a dual opamp can be used to convert a single ended signal into a differential signal for both a bipolar and a unipolar input signal respectively. the voltage applied to point a sets up the common mode voltage. in both diagrams, it is connected in some way to the reference but any value in the common mode range can be input here to setup the common mode. examples of suitable dual opamps that could be used in this configu- ration to provide differential drive to the ad7450a/ AD7440 are the ad8042, ad8056 and the ad8022. care must be taken when chosing the opamp used, as the selection will depend on the required power supply and the system performance objectives. the driver circuits in figures 16(a) and 16(b) are optimized for dc coupling applications requiring optimum distortion performance. the differential op-amp driver circuit in figure 16(a) is configured to convert and level shift a single ended, ground referenced (bipolar) signal to a differential signal centered at the v ref level of the adc. the circuit configuration shown in figure 16(b) converts a unipolar, single ended signal into a differential signal.
rev. pre preliminary technical data ?17? ad7450a/AD7440 gnd 2 x v ref p-to-p 27 ? 27 ? 390 ? 220 ? 220 ? 10k ? external v ref 220 ? v dd v+ v+ v- v- v in+ v in- v ref ad7450a/ AD7440 220 ? 20k ? . . . figure 16(a). dual opamp circuit to convert a single ended bipolar input into a differential input gnd 2 x v ref p-to-p 27 ? 27 ? 390 ? 220 ? 10k ? external v ref 220 ? v dd v+ v+ v- v- v in+ v in- v ref ad7450a/ AD7440 220 ? . . a vref figure 16(b). dual opamp circuit to convert a single ended unipolar input into a differential input rf transformer in systems that do not need to be dc-coupled, an rf trans- former with a center tap offers a good solution for generating differential inputs. figure 17 shows how a transformer is used for single ended to differential conver- sion. it provides the benefits of operating the adc in the differential mode without contributing additional noise and distortion. an rf transformer also has the benefit of providing electrical isolation between the signal source and the adc. a transformer can be used for most ac ap- plications. the center tap is used to shift the differential signal to the common mode level required, in this case it is connected to the reference so the common mode level is the value of the reference. c external v ref (2.5v) r r r v ref v in+ ad7450/ AD7440 v in- 2.5v 3.75v 1.25v 2.5v 3.75v 1.25v figure 17. using an rf transformer to generate differential inputs reference section an external reference source is required to supply the reference to the ad7450a/AD7440. this reference input can range from 100 mv to 3.5 v. with a 5 v power sup- ply, the specified reference is 2.5 v and maximum reference is 3.5 v. with a 3 v power supply, the specified reference is 2 v and the maximum reference is 2.2 v. in both cases, the reference is functional from 100mv. it is important to ensure that, when chosing the reference value for a particular application, the maximum analog input range (vinmax) is never greater than v dd + 0.3v to comply with the maximum ratings of the device. the following two examples calculate the maximum v ref in- put that can be used when operating the ad7450a/ AD7440 at v dd of 5 v and 3.3 v respectively. example 1: vinmax = v dd + 0.3 vinmax = v ref + v ref /2 if v dd = 5 v then vinmax = 5.3 v therefore 3xv ref /2 = 5.3 v v ref max = 3.5 v therefore, when operating at v dd = 5 v, the value of v ref can range from 100mv to a maximum value of 3.5v. when v dd = 4.75 v, v ref max = 3.17 v. example 2: vinmax = v dd + 0.3 vinmax = v ref + v ref /2 if v dd = 3.3v then vinmax = 3.6 v therefore 3xv ref /2 = 3.6 v v ref max = 2.4 v therefore, when operating at v dd = 3.3 v, the value of v ref can range from 100mv to a maximum value of 2.4v. when v dd = 2.7 v, v ref max = 2 v. these examples show that the maximum reference applied to the ad7450a/AD7440 is directly dependant on the value applied to v dd .
rev. pre preliminary technical data ?18? ad7450a/AD7440 the value of the reference sets the analog input span and the common mode voltage range. errors in the reference source will result in gain errors in the ad7450a/AD7440 transfer function and will add to specified full scale errors on the part. a capacitor of 0.1f should be used to decouple the v ref pin to gnd. table i lists examples of suitable voltage references that could be used that are available from analog devices and figure 18 shows a typical connection diagram for the v ref pin. table i examples of suitable voltage references reference output initial operating voltage accuracy current (% max) ( a) ad589 1.235 1.2-2.8 50 ad1580 1.225 0.08-0.8 50 ref192 2.5 0.08-0.4 45 ref43 2.5 0.06-0.1 600 ad780 2.5 0.04-0.2 1000 v ref ad7450/ AD7440* v dd 1 2 3 4 5 6 7 8 vin te m p gnd tr i m vout opsel 0.1f nc nc nc nc vdd 0.1f 0.1f 10nf *additional pins omitted for clarity ad780 2.5 v figure 18. typical v ref connection diagram for v dd = 5 v single ended operation when supplied with a 5 v power supply, the ad7450a/ AD7440 can handle a single ended input. the design of this part is optimized for differential operation so with a single ended input, performance will degrade. linearity will degrade by typically 0.2 lsbs, zero code and the full scale errors will degrade by typically 2 lsbs and ac performance is not guaranteed. to operate the ad7450a/AD7440 in single ended mode, the v in+ input is coupled to the signal source while the v in- input is biased to the appropriate voltage correspond- ing to the mid-scale code transition. this voltage is the common mode, which is a fixed dc voltage (usually the reference). the v in+ input swings around this value and should have voltage span of 2 x v ref to make use of the full dynamic range of the part. the input signal will there- fore have peak to peak values of common mode v ref . if the analog input is unipolar then an opamp in a non- inverting unity gain configuration can be used to drive the v in+ pin. because the adc operates from a single supply, it will be necessary to level shift ground based bipolar signals to comply with the input requirements. an opamp can be configured to rescale and level shift the ground based bipolar signal so it is compatible with the selected input range of the ad7450a/AD7440 (see figure 19). external v ref (2.5v) v in 0v +2.5v -2.5v 0.1f v ref v in+ ad7450/ AD7440 v in- r r r r 0v +2.5v +5v figure 19. applying a bipolar single ended input to the ad7450a/AD7440 serial interface figures 1 and 2 show detailed timing diagrams for the serial interface of the ad7450a and the AD7440 respec- tively. the serial clock provides the conversion clock and also controls the transfer of data from the device during conversion. cs initiates the conversion process and frames the data transfer. the falling edge of cs puts the track and hold into hold mode and takes the bus out of three- state. the analog input is sampled and the conversion initiated at this point. the conversion will require 16 sclk cycles to complete. once 13 sclk falling edges have occurred, the track and hold will go back into track on the next sclk rising edge as shown at point b in figures 20 and 21. on the 16th sclk falling edge the sdata line will go back into three-state. if the rising edge of cs occurs before 16 sclks have elapsed, the conversion will be terminated and the sdata line will go back into three-state. the conversion result from the ad7450a/AD7440 is pro- vided on the sdata output as a serial data streatm. the bits are clocked out on the falling edge of the sclk input. the data stream of the ad7450a consists of four leading zeros, followed by 12 bits of conversion data which is provided msb first; the data stream of the AD7440 consists of four leading zeros, followed by the 10 bits of conversion data, followed by two trailing zeros, which is also provided msb first. in both cases, the output coding is twos complement. 16 serial clock cycles are required to perform a conversion and to access data from the ad7450a/AD7440. cs going low provides the first leading zero to be read in by the micro- controller or dsp. the remaining data is then clocked out on the subsequent sclk falling edges beginning with the second leading zero. thus the first falling clock edge on the serial clock provides the second leading zero. the final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. once the conversion is complete and the data has been accessed after the 16 clock cycles, it is important to ensure that, before
rev. pre preliminary technical data ?19? ad7450a/AD7440 the next conversion is initiated, enough time is left to meet the acquisition and quiet time specifications - see the timing examples. to achieve 1msps with an 18mhz clock for v dd = 3 v and 5 v, an 18 clock burst will perform the conversion and leave enough time before the next conversion for the acquisition and quiet time. in applications with a slower sclk, it may be possible to read in data on each sclk rising edge i.e. the first rising edge of sclk after the cs falling edge would have the leading zero provided and the 15th sclk edge would have db0 provided. timing example 1 having f sclk = 18mhz and a throughput rate of 1msps gives a cycle time of: 1/throughput = 1/1,000,000 = 1s a cycle consists of: t 2 + 12.5 (1/f sclk ) + t acq = 1s. therefore if t 2 = 10ns then: 10ns + 12.5(1/18mhz) + t acq = 1s t acq = 296ns this 296ns satisfies the requirement of 200ns for t acq . from figure 20, t acq comprises of: 2.5(1/f sclk ) + t 8 + t quiet where t 8 = 35ns. this allows a value of 122ns for t quiet satisfying the minimum requirement of 25ns. timing example 2 having f sclk = 5mhz and a throughput rate of 315ksps gives a cycle time of : 1/throughput = 1/315000 = 3.174s a cycle consists of: t 2 + 12.5 (1/f sclk ) + t acq = 3.174s. therefore if t 2 is 10ns then: 10ns + 12.5(1/5mhz) + t acq = 3.174s t acq = 664ns this 664ns satisfies the requirement of 200ns for t acq . from figure 20, t acq comprises of: 2.5(1/f sclk ) + t 8 + t quiet where t 8 = 35ns. this allows a value of 129ns for t quiet satisfying the minimum requirement of 25ns. as in this example and with other slower clock values, the signal may already be acquired before the conversion is complete but it is still necessary to leave 25ns minimum t quiet between conversions. in example 2 the signal should be fully acquired at approximately point c in figure 20. modes of operation the mode of operation of the ad7450a/AD7440 is selected by controlling the logic state of the cs signal during a conversion. there are two possible modes of operation, normal mode and power-down mode. the point at which cs is pulled high after the conversion has been initiated will determine whether or not the ad7450a/AD7440 will enter the power-down mode. similarly, if already in power-down, cs controls whether the devices will return to normal operation or remain in power-down. these modes of operation are designed to provide flexible power manage- ment options. these options can be chosen to optimize the power dissipation/throughput rate ratio for differing applica- tion requirements. normal mode this mode is intended for fastest throughput rate perfor- mance. the user does not have to worry about any power-up times with the ad7450a/AD7440 remaining fully powered up all the time. figure 21 shows the gen- eral diagram of the operation of the ad7450a/AD7440 in this mode. the conversion is initiated on the falling edge of cs as described in the ?serial interface section?. to ensure the part remains fully powered up, cs must remain low until at least 10 sclk falling edges have elapsed after the falling edge of cs . if cs is brought high any time after the 10th sclk fall- ing edge, but before the 16th sclk falling edge, the part will remain powered up but the conversion will be termi- nated and sdata will go back into three-state. sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. cs may idle high until the next conversion or may idle low until some- time prior to the next conversion. once a data transfer is complete, i.e. when sdata has returned to three-state, another conversion can be initiated after the quiet time, t quiet has elapsed by again bringing cs low. figure 20. serial interface timing example 1 2345 13 16 15 14 t 2 t 6 t 5 t 8 t quiet convert t b t acquisition 12.5(1/f sclk ) 1/throughput 10ns sclk c
rev. pre preliminary technical data ?20? ad7450a/AD7440 4 leading zeros + conversion result sdata 10 16 sclk 1 figure 21. normal mode operation power down mode this mode is intended for use in applications where slower throughput rates are required; either the adc is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and the adc is then powered down for a relatively long duration between these bursts of several conversions. when the ad7450a/AD7440 is in the power down mode, all analog circuitry is powered down. to enter power down mode, the conversion process must be interrupted by bringing cs high anywhere after the second falling edge of sclk and before the tenth falling edge of sclk as shown in figure 22. three state sclk sdata 12 10 figure 22. entering power down mode once cs has been brought high in this window of sclks, the part will enter power down and the conver- sion that was initiated by the falling edge of cs will be terminated and sdata will go back into three-state. the time from the rising edge of cs to sdata three- state enabled will never be greater than t 8 (see the ?timing specifications?). if cs is brought high before the second sclk falling edge, the part will remain in normal mode and will not power-down. this will avoid accidental power-down due to glitches on the cs line. in order to exit this mode of operation and power the ad7450a/AD7440 up again, a dummy conversion is per- formed. on the falling edge of cs the device will begin to power up, and will continue to power up as long as cs is held low until after the falling edge of the 10th sclk. the device will be fully powered up after 1sec has elapsed and, as shown in figure 23, valid data will result from the next conversion. if cs is brought high before the 10th falling edge of sclk, the ad7450a/AD7440 will again go back into power-down. this avoids accidental power-up due to glitches on the cs line or an inadvertent burst of eight sclk cycles while cs is low. so although the device may begin to power up on the falling edge of cs , it will again power-down on the rising edge of cs as long as it occurs before the 10th sclk falling edge. power up time the power up time of the ad7450a/AD7440 is typically 1sec, which means that with any frequency of sclk up to 18mhz, one dummy cycle will always be sufficient to allow the device to power-up. once the dummy cycle is complete, the adc will be fully powered up and the input signal will be acquired properly. the quiet time t quiet must still be allowed from the point at which the bus goes back into three-state after the dummy conversion, to the next falling edge of cs . when running at the maximum throughput rate of 1msps, the ad7450a/AD7440 will power up and ac- quire a signal within 0.5lsb in one dummy cycle, i.e. 1s. when powering up from the power-down mode with a dummy cycle, as in figure 23, the track and hold, which was in hold mode while the part was powered down, re- turns to track mode after the first sclk edge the part receives after the falling edge of cs . this is shown as point a in figure 23. although at any sclk frequency one dummy cycle is sufficient to power the device up and acquire v in , it does not necessarily mean that a full dummy cycle of 16 sclks must always elapse to power up the device and acquire v in fully; 1s will be sufficient to power the de- vice up and acquire the input signal. for example, if a 5mhz sclk frequency was applied to the adc, the cycle time would be 3.2s (i.e. 1/(5mhz) x 16). in one dummy cycle, 3.2s, the part would be pow- ered up and v in acquired fully. however after 1s with a 5mhz sclk only 5 sclk cycles would have elapsed. at this stage, the adc would be fully powered up and the signal acquired. so, in this case the cs can be brought high after the 10th sclk falling edge and brought low again after a time t quiet to initiate the conversion. when power supplies are first applied to the ad7450a/ AD7440, the adc may either power up in the power- down mode or normal mode. because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. like- wise, if the user wishes the part to power up in power-down mode, then the dummy cycle may be used to ensure the device is in power-down by executing a cycle such as that shown in figure 22. once supplies are applied to the ad7450a/AD7440, the power up time is the same as that when powering up from the power-down mode. it takes approximately 1s to power up fully if the part powers up in normal mode. it is not necessary to wait 1s before executing a dummy cycle to ensure the desired mode of operation. instead, the dummy cycle can occur directly after power is supplied to the adc. if the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. as mentioned earlier, when powering up from the power- down mode, the part will return to track upon the first
rev. pre preliminary technical data ?21? ad7450a/AD7440 sclk edge applied after the falling edge of cs . how- ever, when the adc powers up initially after supplies are applied, the track and hold will already be in track. this means if (assuming one has the facility to monitor the adc supply current) the adc powers up in the desired mode of operation and thus a dummy cycle is not required to change mode, then neither is a dummy cycle required to place the track and hold into track. power versus throughput rate by using the power-down mode on the ad7450a/AD7440 when not converting, the average power consumption of the adc decreases at lower throughput rates. figure 24 shows how, as the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption reduces accordingly. it shows this for both 5v and 3v power supplies. for example, if the ad7450a/AD7440 is operated in continuous sampling mode with a throughput rate of 100ksps and an sclk of 18mhz and the device is placed in the power down mode between conversions, then the power consumption is calculated as follows: power dissipation during normal operation = 9mw typ (for v dd = 5v). if the power up time is 1 dummy cycle i.e. 1sec, and the remaining conversion time is another cycle i.e. 1sec, then the ad7450a/AD7440 can be said to dissipate 9mw for 2sec* during each conversion cycle. if the throughput rate = 100ksps then the cycle time = 10sec and the average power dissipated during each cycle is: (2/10) x 9mw = 1.8mw for the same scenario, if v dd = 3v, the power dissipation during normal operation is 3.75mw max. the ad7450a/AD7440 can now be said to dissipate 3.75mw for 2sec* during each conversion cycle. the average power dissipated during each cycle with a throughput rate of 100ksps is therefore: (2/10) x 3.75mw = 0.75mw this is how the power numbers in figure 24 are calcu- lated. for throughput rates above 320ksps, it is recommended that for optimum power performance, the serial clock frequency is reduced. figure 24. power versus throughput rate for power down mode *this figure assumes a very short time used to enter the power down mode. this will increase as the burst of clocks used to enter the power down mode is increased. microprocessor and dsp interfacing the serial interface on the ad7450a/AD7440 allows the part to be directly connected to a range of different micro- processors. this section explains how to interface the ad7450a/AD7440 with some of the more common microcontroller and dsp serial interface protocols. ad7450a/AD7440 to adsp21xx the adsp21xx family of dsps are interfaced directly to the ad7450a/AD7440 without any glue logic required. the sport control register should be set up as follows: tfsw = rfsw = 1, alternate framing invrfs = invtfs = 1, active low frame signal dtype = 00, right justify data slen = 1111, 16-bit data words isclk = 1, internal serial clock tfsr = rfsr = 1, frame every word irfs = 0, itfs = 1. to implement the power-down mode slen should be set to 1001 to issue an 8-bit sclk burst. figure 23. exiting power down mode sdata invalid data sclk 116 valid data 1 a the part begins to power up the part is fully powered up with vin fully acquired 10 10 16 t powerup
rev. pre preliminary technical data ?22? ad7450a/AD7440 the connection diagram is shown in figure 25. the adsp21xx has the tfs and rfs of the sport tied together, with tfs set as an output and rfs set as an input. the dsp operates in alternate framing mode and the sport control register is set up as described. the frame synchronisation signal generated on the tfs is tied to cs and as with all signal processing applications equidistant sampling is necessary. however, in this ex- ample, the timer interrupt is used to control the sampling rate of the adc and under certain conditions, equidistant sampling may not be acheived. ad7450a/AD7440* sclk sdata sclk dr rfs tfs adsp21xx* *additional pins omitted for clarity figure 25. interfacing to the adsp 21xx the timer registers etc., are loaded with a value which will provide an interrupt at the required sample interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to con- trol the rfs and hence the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given, (i.e. ax0=tx0), the state of the sclk is checked. the dsp will wait until the sclk has gone high, low and high before transmission will start. if the timer and sclk val- ues are chosen such that the instruction to transmit occurs on or near the rising edge of sclk, then the data may be transmitted or it may wait until the next clock edge. for example, the adsp-2111 has a master clock fre- quency of 16mhz. if the sclkdiv register is loaded with the value 3 then a sclk of 2mhz is obtained, and 8 master clock periods will elapse for every 1 sclk period. if the timer registers are loaded with the value 803, then 100.5 sclks will occur between interrupts and subse- quently between transmit instructions. this situation will result in non-equidistant sampling as the transmit instruc- tion is occuring on a sclk edge. if the number of sclks between interrupts is a whole integer figure of n then equidistant sampling will be implemented by the dsp. ad7450a/AD7440 to tms320c5x/c54x the serial interface on the tms320c5x/c54x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the ad7450a/AD7440. the cs input allows easy interfacing between the tms320c5x/c54x and the ad7450a/AD7440 without any glue logic required. the serial port of the tms320c5x/c54x is set up to operate in burst mode with internal clkx (tx serial clock) and fsx (tx frame sync). the serial port control register (spc) must have the following setup: fo = 0, fsm = 1, mcm = 1 and txm = 1. the format bit, fo, may be set to 1 to set the word length to 8-bits, in order to imple- ment the power-down mode on the ad7450a/AD7440. the connection diagram is shown in figure 26. it should be noted that for signal processing applications, it is im- perative that the frame synchronisation signal from the tms320c5x/c54x will provide equidistant sampling. ad7450a/AD7440* sclk sdata clkx fsr tms320c5x/c54x* *additional pins omitted for clarity clkr dr fsx figure 26. interfacing to the tms320c5x/c54x ad7450a/AD7440 to mc68hc16 the serial peripheral interface (spi) on the mc68hc16 is configured for master mode (mstr = 1), clock polar- ity bit (cpol) = 1 and the clock phase bit (cpha) = 0. the spi is configured by writing to the spi control reg- ister (spcr) - see 68hc16 user manual. the serial transfer will take place as a 16-bit operation when the size bit in the spcr register is set to size = 1. to implement the power-down modes with an 8-bit transfer set size = 0. a connection diagram is shown in figure 27. ad7450a/AD7440* sdata * *additional pins omitted for clarity miso/pmc0 sclk/pmc2 sclk ss/pmc3 mc68hc16* figure 27. interfacing to the mc68hc16 ad7450a/AD7440 to dsp56xxx the connection diagram in figure 28 shows how the ad7450a/AD7440 can be connected to the ssi (synchro- nous serial interface) of the dsp56xxx family of dsps from motorola. the ssi is operated in synchronous mode (syn bit in crb =1) with internally generated 1- word frame sync for both tx and rx (bits fsl1 =0 and fsl0 =0 in crb). set the word length to 16 by setting bits wl1 =1 and wl0 = 0 in cra. to implement the power-down mode on the ad7450a/AD7440 then the word length can be changed to 8 bits by setting bits wl1 = 0 and wl0 = 0 in cra. it should be noted that for signal processing applications, it is imperative that the frame synchronisation signal from the dsp56xxx will provideequidistant sampling.
rev. pre preliminary technical data ?23? ad7450a/AD7440 ad7450a/AD7440* sdata * *additional pins omitted for clarity srd sclk sclk sr2 dsp56xxx* figure 28. interfacing to the dsp56xx application hints grounding and layout the printed circuit board that houses the ad7450a/ AD7440 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is gener- ally best for ground planes as it gives the best shielding. digital and analog ground planes should be joined in only one place and the connection should be a star ground point established as close to the gnd pin on the ad7450a/AD7440 as possible. avoid running digital lines under the device as this will couple noise onto the die. the analog ground plane should be allowed to run under the ad7450a/AD7440 to avoid noise coupling. the power supply lines to the ad7450a/AD7440 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power sup- ply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. avoid crossover of digital and analog sig- nals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double- sided board. in this technique the component side of the board is dedi- cated to ground planes while signals are placed on the solder side. good decoupling is also important. all ana- log supplies should be decoupled with 10f tantalum capacitors in parallel with 0.1f capacitors to gnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device. evaluating the ad7450a/AD7440 performance the evaluation board package includes a fully assembled and tested evaluation board, documentation and software for controlling the board from a pc via the evaluation board controller. the evaluation board controller can be used in conjunction with the ad7450a/40 evaluation board as well as many other analog devices evaluation boards ending with the cb designator, to demonstrate/ evaluate the ac and dc performance of the ad7450a/40. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad7450a/40. see the evaluation board technical note for more information.
rev. pre preliminary technical data ?24? ad7450a/AD7440 outline dimensions dimensions shown in inches (millimeters) 8-lead sot-23 (rt-8) 8-lead msop (rm-8) 1234 8765 0.122 (3.10) 0.110 (2.80) pin 1 0.077 (1.95) bsc 0.026 (0.65) bsc 0.071 (1.80) 0.059 (1.50) 0.009 (0.23) 0.003 (0.08) 0.022 (0.55) 0.014 (0.35) 10 8 0 8 0.015 (0.38) 0.009 (0.22) 0.006 (0.15) 0.000 (0.00) 0.051 (1.30) 0.035 (0.90) seating plane 0.057 (1.45) 0.035 (0.90) 0.118 (3.0) 0.098 (2.50)

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